NXP Semiconductors /MIMXRT1052 /IOMUXC /SW_MUX_CTL_PAD_GPIO_SD_B0_02

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Interpret as SW_MUX_CTL_PAD_GPIO_SD_B0_02

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_SD_B0_02 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1

1 (ALT1): Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1

2 (ALT2): Select mux mode: ALT2 mux port: LPUART8_CTS_B of instance: lpuart8

3 (ALT3): Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1

4 (ALT4): Select mux mode: ALT4 mux port: LPSPI1_SDO of instance: lpspi1

5 (ALT5): Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_SD_B0_02

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